A semiconductor memory device typically includes a plurality of unit cells for storing a plurality of data. A DRAM, which is a widely used semiconductor memory device, includes a capacitor configured to accumulate charges therein for storing data. In the DRAM, a unit cell includes a capacitor and a MOS transistor serving as a switch.
Due to development of semiconductor techniques, a memory device has been manufactured to operate at a high speed for high integration. Specifically, for high integration of the DRAM, it is necessary to reduce an area of a cell block consisting of a plurality of unit cells occupying the area.
The capacitor is configured to accumulate the minimum charge amount so that data may be maintained. Since the charge amount stored in the capacitor is very small, a bit line sense amplifier unit amplifies a signal for maintaining data stored in the unit cell and outputs the signal externally.
A memory cell array having an open bit line structure has been used where a unit cell corresponds to a bit lint sense amplifier. However, due to high integration of the DRAM, it is difficult to arrange a unit cell including a capacitor and a MOS transistor corresponding to a bit line sense amplifier including four MOS transistors.
In the memory cell array having an open bit line structure, a bit line BL connected to the bit line sense amplifier is connected to a cell block. A bit line bar /BL connected to the bit line sense amplifier is connected to the other cell block. As a result, an area occupied by the bit line sense amplifier may be increased in the memory cell array.
In order to reduce the area, a folded bit line structure has been suggested where a bit line sense amplifier is connected to two unit cells. The folded bit line structure refers to a structure where a bit line BL is arranged in parallel to a bit line bar /BL and a bit line sense amplifier is connected to two unit cells.
FIG. 1 is a circuit diagram illustrating a cell array of a general DRAM. FIG. 1 shows a folded bit line structure and a latch-type bit line sense amplifier.
A unit cell C of a DRAM includes a NMOS transistor T1 regulated by a word line WL0 and a capacitor C1. The NMOS transistor T1 has a drain connected to a bit line BL, and a source connected to an electrode of the capacitor C1. One electrode of capacitor C1 is defined by a storage node SN where written charges are stored.
The other electrode of capacitor C1 is connected to a common cell plate line PL to receive a cell plate voltage VCP. Cell plate voltage VCP is defined by a half power voltage VDD. Power voltage VDD is defined by a high operating voltage of the cell.
Both output terminals of the latch-type bit line sense amplifier are connected to paired bit lines BL, /BL. When word line WL0 is activated to transmit cell data into true bit line BL, complement bit line /BL supplies a reference voltage REF. When a word line WL1 is activated to transmit cell data into the complement bit line /BL, true bit line BL supplies reference voltage REF.
A pair of local data buses LDB, LDBB are configured to input/output data of a data buffer and the bit line sense amplifier S/A.
FIG. 2 is a circuit diagram illustrating a latch-type bit line sense amplifier of a general DRAM.
The latch-type bit line sense amplifier includes equalizing units 10, 22, bit line selecting units 12, 18, a bit line precharging unit 14, an amplifying unit 16 and a selecting unit 20.
Equalizing units 10, 22 are configured to equalize a voltage between the paired bit lines BL, /BL in response to a bit line equalizing signal BLEQ. Bit line selecting units 12, 18 are configured to exchange data between paired bit lines BL, /BL with amplifying unit 16 in response to bit line selecting signals BISH, BISL.
Bit line precharging unit 14 supplies a bit line precharge voltage VBLP to paired bit lines BL, /BL with bit line equalizing signal BLEQ so as to precharge paired bit lines BL, /BL. Bit line precharge voltage VBLP is defined by a half power voltage VDD.
A pull-up activating terminal of amplifying unit 16 is regulated by a control signal SAP, and a pull-down activating terminal is regulated by a control signal SAN. Amplifying unit 16 senses and amplifies data applied to paired bit lines BL, /BL. Selecting unit 20 controls input/output operations of data between bit line sense amplifier unit 16 and paired local data buses LDB, LDBB in response to a column selecting signal YI.
FIG. 3 is a timing diagram illustrating a cell array and a sensing-related operation of a general DRAM.
In a precharge period t0, a voltage of paired bit lines BL, /BL and bit line sense amplifier control signals SAN, SAP are precharged to bit line precharge voltage VBLP. Bit line precharge voltage VBLP is defined by half power voltage VDD and by a half voltage value of a cell high voltage VDD.
In a period t1 for charge sharing, word line WL is activated to transmit cell data into paired bit lines BL, /BL.
In a period t2 for sensing and amplifying data, control signal SAN for amplifying data of paired bit lines BL, /BL transits to a ground voltage, and control signal SAP transits to cell high voltage VDD. Paired bit lines BL, /BL are amplified to cell high voltage VDD and the ground voltage.
In a period t3 for restoring data, the data amplified in paired bit lines BL, /BL are re-written in the cell. After the restoring operation, a precharge period t4 starts.
A DRAM having a 1-Transistor 1-Capacitor (1T1C) structure reads/writes data using a voltage sensing method. A charge and discharge voltage difference in the bit lines is sensed to sense data. By pull-up/pull-down operations of voltages, data are written in the memory cell to cause a swing operation of a main bit line voltage. As a result, the sensing speed of data is degraded, and a large current is required when data are sensed.